Phase-locked loops (PLL's) have been widely used in high-speed communication systems because PLL's efficiently perform clock recovery or clock generation at a relatively low cost. PLL's used in systems to generate clocks are required to generate low-noise or low jitter clock signals. Conventional analog PLL's may use a narrow-band loop filter to reduce output jitter at the expense of extended locking time. In order to improve locking-time characteristics, digital or hybrid analog/digital PLL's have been used which employ varying algorithms to modify loop bandwidth depending on whether a frequency lock is being acquired or maintained.
For low power microprocessor and handheld device applications it is desirable to shut off the unit's clock generator for power savings. However, the time required for the unit to “wake-up” may be excessive since a phase-locked loop (PLL) clock source may require a long period of time to achieve the desired steady-state conditions. Conventional design approaches for a PLL may reduce acquisition time (i.e., the time required to achieve frequency and phase locked conditions from an initially unlocked state) at the expense of steady state jitter, but this will increase the system cycle time budget. Adaptive PLL techniques have been reported, but often include complex system issues, require additional custom circuit designs, or involve higher-jitter digital PLL techniques.
There is, therefore, a need for a simple adaptive PLL that has fast acquisition time and low jitter while requiring simple hardware to implement.